AN EFFICIENT ALGORITHM FOR WRAPPER AND TAM CO-OPTIMIZATION TO REDUCE TEST APPLICATION TIME IN CORE BASED SOC

System-on-Chip (SOC) designs composed of many embedded cores are ubiquitous in today’s integrated circuits. Each of these cores requires to be tested separately after manufacturing of the SoC. That’s why, modular testing is adopted for core-based SoCs, as it promotes test reuse and permits the cores to be tested without comprehensive knowledge about their internal structural details. Such modular testing triggers the need of a special test access mechanism (TAM) to build communication between core I/Os and TAM and promises to minimize overall test time. In this paper, various issues are analyzed to optimize the Wrapper and TAM, which comprises the optimal partitioning of TAM width, assignment of cores to partitioned TAM width etc.