DESIGNING PHASE FREQUENCY DETECTOR USING DIFFERENT DESIGN TECHNOLOGIES

This paper presents the designs of phasefrequency detector. The simulation results are focused on accounting thefrequency operation, power dissipation and noise. The various PFDs are designedusing 0.35 μm CMOS technology on SPICE simulator with 3.3 V supply voltage. Thetransfercurve of the different logic designed PFDs shows thatthe mentioned designs are dead zone free. In the first section, a basicintroduction about phase locked loop and the importance of PFD is discussed. Inthe second section, a brief description about the different logic designs usedin this paper is given. Subsequently, in the third section, simulation resultsof various models optimized are observed, explained and finally based on theseobservations results have been concluded at the end.