Design of 64-Bit Decode Stage for VLIW Processor Architecture

? VLIW stands for Very Long Instruction Word. This Processor Architecture is based on parallel processing in which more than one instructions are executed in parallel. This architecture is used to increase the instruction throughput. So this is the base of the modern Superscalar Processors. Basically VLIW is a RISC Processor. The difference is it contains long instruction as compared to RISC. During the execution of the program the operands are stored in the General Purpose Register File. Register file is the combination of registers. Depending upon the processor architecture the number of registers inside the register file can be varies. Here the design of 64 bit decode stage. This stage of the pipeline decodes the instruction fetched by the fetch stage. The decode stage also fetches register data from the register file and register the operand is transfer is decided by the five bit address. Now to generate the gate level netlist Synthesis is done on Xilinx ISE 13.1 by taking Virtex 4 FPGA with 4vfx12sf363 package with speed grade -12.After the synthesis the total memory usage is 200332 kilobytes and the number of bonded IOBs are 435. Decode stage are synthesized and targeted for Xilinx Virtex 4 FPGA and the results calculated for 64-bit decode stage improve the speed as compared to previous work done.