FPGA VERIFICATION OF MODIFIED REPETITIVE CONTROLLER FOR A POWER QUALITY CONDITIONER

Simulations and prototyping have been a very important part of the electronics industry since a very long time. In recent years, FPGA‘s have become increasingly important and have found their way into all kind of digital system design. This paper presents a novel, easy and efficient approach for generation and verification of VHDL code for a modified repetitive controller, for limiting the fault current in a distribution line and to compensate key voltage - quality disturbances namely; voltage sags, harmonic voltages, voltage imbalances. The control structure is quite simple and yet very robust. The MATLAB HDL coder is used for generating a VHDL code from a working MATLAB model and the generated code is verified in MODELSIM simulator.