Reduction of the surface roughness of Ge-on-insulator layers up to sub-nanometer range by chemical mechanical polishing

We are investigating the thermoelectric characteristics of Ge and SiGe nanostructures for realizing high power generator efficiency. In this paper, we investigated the influence of the thinning process on the surface roughness of a direct wafer- bonded p-type Ge-on-insulator (GOI) layer in order to realize an ultra-thin GOI substrate with extremely low surface roughness for the fabrication of Ge and SiGe nanostructures. The wafer thinning process was performed by chemical mechanical polishing (CMP) and wet chemical etching (WCE). A very smooth GOI layer with sub-nanometer (0.3 nm) surface roughness, suitable for nanostructure fabrication, was achieved using CMP compared to WCE process.