Analysis and Modeling of Low Power Array Multipliers Using Cadence Virtuoso Tool in 45 NM Technology

The increasing demand for the high fidelity portable devices has laid emphasis on the development of low power and high performance systems. In the next generation processors, the low power design has to be incorporated into fundamental computation units, such as multipliers. The characterization and optimization of such low power multipliers will aid in comparison and choice of multiplier modules in system design. In this paper we performed a comparative analysis of the power, delay, and power delay product (PDP) optimization characteristics of five parallel digital multipliers implemented using low power 10 transistor (10T) Adder. Multipliers realized using the 10T Adder circuit because 10T Adder consumed considerably less power compared to Static Energy Recovery Full adder (SERF) and static CMOS Adder for all the configurations studied., design of five different array multipliers are presented. The multipliers presented in this paper were all modeled using Cadence Tools (Virtuoso Simulator). The comparison is done on the basis of three performance parameters i.e. Area, Speed and Power consumption. The difference between the power consumption of the 10 transistor based multipliers is significant at 45 nm. For smaller geometry sizes down to 45 nm, the propagation delay of the multipliers implemented with 10 transistors translates to a better performance measure. This can be attributed to the fast computational capability of the CSA multiplier and 10T adder logic saving more power at deep sub-micron sizes. The proposed SERF-10T Hybrid adder model multipliers consumed the least power of all the Hybrid and regular models with no deterioration in performance. Taken together, these results suggest that SERF-10T Hybrid model based multipliers are suited for ultra low power design and fast computation at smaller geometry sizes.