Cost Analysis and Simulation of Decimator for Multirate Applications
Journal: INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY (Vol.11, No. 1)Publication Date: 2013-12-05
Authors : Rajesh Mehra; Lajwanti Singh;
Page : 2175-2181
Keywords : ASIC; Decimator; DSP; FIR; FPGA .;
Abstract
In this paper, a decimator design has been presented for multirate digital signal processing. ?The decimator design has been analysed and simulated for cost comparison in terms of multipliers and MPIS. Two structures ?namely Transposed Direct form and Symmetric Direct form have been used performance and ?resource consumption analysis. The decimators have been designed ?& simulated using MATLAB. It can be observed from the simulated results that symmetric structure comsumes almost 50% less multipliers and MPIS compared to transposed structure. So the symmetric structure based decimator is suitable to provide cost effective solution
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