INTERFACING OF SYSTEMVERILOG AND SYSTEMC USING TRANSACTION LEVEL MODELING
Journal: INTERNATIONAL JOURNAL OF COMPUTERS & DISTRIBUTED SYSTEMS (Vol.4, No. 2)Publication Date: 2014-02-28
Authors : Vishnu Satya Chaitanya Chittoor; Sundaresan C; Prem Kumar Lohani; Ranjani K; Ravi Shankar R;
Page : 51-63
Keywords : SystemVerilog; SystemC; TLM; Interface; VLSI; Verification.;
Abstract
SystemVerilog and SystemC are extensively used for design and Verification in VLSI industry. This paper propose a method to combine SystemVerilog and SystemC code in a single hardware/software simulation which allows design teams to leverage abstract representations of system function as it increases system simulations speed. ?This paper also purposes a method of developing generalized Noise Channel Model to mimic the real timing scenarios in communication protocols and provide physical medium timing information to higher layers using SystemC.
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