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Cache Memory Organization

Journal: INTERNATIONAL JOURNAL OF NETWORKING AND PARALLEL COMPUTING (Vol.1, No. 2)

Publication Date:

Authors : ;

Page : 12-16

Keywords : SRAM; DRAM; DMA; MESI;

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Abstract

Computer memory is organized into a hierarchy. At the highest level are the processor registers, next comes one or more levels of cache , main memory, which is usually made out of a dynamic random-access memory (DRAM) and at last external memory composed of magnetic disks and tapes. All of these are considered internal to the computer system. Cache is small high speed memory usually Static RAM (SRAM) that contains the most recently accessed pieces of main memory. Cache memories are the high speed buffers which are interested between the processors and main memory to capture those portion of the contents of the main memory which are currently in use. Since cache memories are typically 5 -10 times faster than main memory they can reduce the effective memory access time if carefully designed and implemented. In this paper, we are going to discuss the architectural specification, cache mapping techniques, write policies, performance optimization in detail with case study of Pentium processors implementing cache.

Last modified: 2016-07-04 16:58:37