Design and Simulation of 32 bit Floating Point FFT Processor Using VHDLJournal: IPASJ International Journal of Electronics & Communication (IIJEC) (Vol.4, No. 6)
Publication Date: 2016-07-05
Authors : Roshan Pahune; Dr.Mrs.AnaghaRathkanthiwar;
Page : 18-25
Keywords : KEYWORDS :-Floating Point Number; FFT; DIT; Radix-2; VHDL.;
ABSTRACT FFT & IFFT algorithms has gainedlot of importance since use of OFDM technology in communication system. OFDM technology is implemented using FFT & IFFT. We are here with presenting thedesign of a 32 bit floating point FFT processor. For design and implementation of FFT processor we have consider radix-2 DITFFT algorithm. The floating point number can support wide range of values. It is represented using three fields: sign, exponent and mantissa. In this paper floating point addition, subtraction and multiplication algorithms for IEEE-754 (single precision)is used. The IEEE-754 converter is used to convert decimal floating point number into IEEE Binary floating point format and it is also used to verify the results. For performance measurement of this design, various parameters like number of flip flops, number of LUTs, delay and complexity are obtained. The results are compared with existing design and are presented in this paper.
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Last modified: 2016-07-05 19:53:20