Correction of Multiple Errors with Seamless Pipeline Operation Using AHL

A low power flip-flop (FF) design featuring an explicit type-pulsed triggered structure and a modified true signal phase clock latch based on a signal feed through scheme is presented. The proposed design successfully solves the long discharging path problem in seamless pipeline operation and achieves better speed and power performance. If error will be happen in any received data, the entire clock will be stop because of razor based shadow latch flip-flop skip the entire portions. So, I had to add AHL a keeper technique. Here I designed the circuit as error occurred at the pipeline is transferred to AHL it contains some process to clear the error and continue to the pipeline.