UVM ARCHITECTURE FOR VERIFICATION

The System Verilog UVM promises to improve verification productivity while enabling teams to share tests and test benches between projects and divisions. This promise can be achieved; the UVM is a powerful methodology for using constrained randomization to reach higher functional coverage goals and to explore combinations of tests without having to write each one individually. Unfortunately the UVM promise can be hard to reach without training, practice and some significant expertise. Verification is one of the most important activities in the flow of ASIC/VLSI design. Verification consumes large amount of design flow cycle & efforts to ensure design is bug free. Hence it becomes intense requirement for powerful and reusable methodology for verification. The Universal Verification Methodology (UVM) is a powerful verification methodology that may be used to verify a wide range of design sizes and types. UVM is derived from other methodology like VMM, OVM, eRM. It is useful to verify designs in any language like Verilog, VHDL, System Verilog. Reusable verification environment is possible using UVM & hence saving considerable time in Verification cycle. This paper talks about the architecture of environment using UVM. It also focuses on terms & ways used in Verification using UVM.