DESIGN AND DEVELOPMENT OF MEMORY MANAGEMENT UNIT FOR MIL-STD-1750 PROCESSOR

Processor Interface ASIC (PI ASIC) was widely used to provide processor interface logics for MAR31750 Processor along with MA31751 Memory Management Unit (MMU) chip. However with the diminishing availability of MA31750 processors, use of the Mil-Std -1750 processor of Honeywell make ? HX1750 as a replacement for the obsolete MAR 31750 Since HX-1750 processor does not have a compatible COTS MMU chip available, it was decided to functionality of the existing MMU chip (MA31751) onto an FPGA The remaining regular processor interface logics, similar to those in PI ASIC are also housed inside the Processor Interface FPGA. Considering the voluminous size of requirements, RTAX-1000S FPGA was chosen to implement the processor interface logics. With a system clock of 24MHz and an internal MMU inside the FPGA the cycle time for memory accesses has considerably been reduced. The embedded SRAM blocks of the RTAX-1000S FPGA are used as shared RAM between CPU and the 1553 device.