Improving Code Compression Efficiency of MIPS32 Processor using Modified ISA

Embedded systems place major role in real world technology. In this memory and code size minimization reduces the complexity of the system. Code compression techniques address this issue by reducing the code size of application programs .Large code occupies more space in the Chip and also causes higher power consumption because of increased memory traffic. In this paper, a modified architecture is proposed for MIPS32 processor by replacing the Load-store Architecture with Register-store Architecture for some of the instructions. Using Simple Scalar performance simulator we achieved 67.5% of compression efficiency for MIPS32 processor with the help of modified ISA.