Analysis of Cache Memory Performance Variation on Size Variation
Journal: INTERNATIONAL JOURNAL OF HUMANITIES & INFORMATION TECHNOLOGY (IJHIT) (Vol.1, No. 1)Publication Date: 2016-01-30
Authors : Dharmesh K. Raman;
Page : 2-7
Keywords : Spatial Locality; Temporal Locality; CPU; Intel Cache; Data Buffer;
Abstract
Abstract: Caches are introduced into a system to buffer the mismatch between main memory and processor speeds. A cache is a relatively small, fast memory placed between the processor and the main memory. The cache is designed so that its access time matches the processor cycle time. Thus, if the processor is running with a 100MHz clock the cache should be able to respond to a memory request in approximately 10ns. In the high-performance single-chip processors being built today, the cache memory is actually built on the processor chip and separated into distinct instruction and data caches. The typical size of these caches is 8kb, for a total of 16kb of cache on the processor chip. Many system designs also include an off-chip cache, which is called the second-level cache or the L2 cache: Keywords: Spatial Locality, Temporal Locality, CPU, Intel Cache, Data Buffer
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