A Digital Error Correction Technique for the Resettable Delta-Sigma Modulator Used in a Multiple-Sampling Based High-Resolution ADC

:This paper presents a technique for digital error correction of the nonlinearity due to capacitor mismatch and finite gain error of operational amplifier in the first-order resettable delta-sigma modulator (RDSM) used in a multiple-sampling based high-resolution ADC. The effectiveness of the digital error correction is confirmed by using circuit simulation data with 65 nm technology parameters. The simulation results show that the digital error correction improves the integral nonlinearity (INL) from +4.52/-4.58 LSB to +0.30/-0.45 LSB at 12bits.