DESIGN AND DEVELOPMENT OF HYBRID MAC BASED ON CSCS

FPGA based MAC has evolved into significant research field within engineering that encompasses the science of signal processing for developing a real-time digital analysis system. Due to the dynamic nature of applications, the MAC unit should offer low processing time and high resource optimization. In this paper, we propose novel multiplier-accumulator (MAC) hybrid architecture based on CSA with focus on development and advancement involving image/video processing based algorithms and other digital constraints. Many of the existing approaches rely on basic factor multiplication and accumulation as separate entities which would increasing the resources and time. An essential factor in effective design of novel MAC unit is the incorporation of multiplication and accumulation as single entity with accuracy and reduced cost. Further, application requires the minimum possible delay based on well defined principles. Unfortunately, MAC based on the existing approaches has high delay due to accumulator despite the large scale research and models. Henceforth, we incorporated Carry Save Adder (CSA) technique along with several parametric constraints to ensure the feasibility, effectiveness and efficiency of the proposed framework in comparison with the existing methods. The novel structure of CSA exploits the radix-2 based 1’s complement with benefits of altered Booth’s Algorithm that address the sign expansion while minimizing the bits requirement based on operation constraints. The simulations analysis was carried out using ModelSim for conceptual analysis and Xilinx for feasibility analysis of the concept.