Future MOSFET Devices using high-k (TiO2) dielectric

In this paper, an 80nm NMOS with high-k (TiO2) was designed and fabricated to study its electrical characteristics. ATHENA & ATLAS module of SILVACO software are used in simulating the electrical performance of the transistor. The parameters under simulation were the threshold voltage (Vt), Id-Vg & Id-Vd Characteristics. High-k gate technology is a strong alternative for replacing the conventional SiO2 gates in MOSFETs for both high performance and low power applications. High-k oxides offer a solution to leakage problems that occurs as the gate oxide thickness is scaled down. Non-ideal effects such as short channel effects mainly channel modulation and drain induced barrier lowering (DIBL) are investigated in it. It is observed in the results that the threshold voltage could be varied by changing the above mentioned device parameters. The effectiveness is also observed on performance parameters of the MOSFET such as drain induced barrier lowering, sub-threshold slope and threshold voltage. Hence device engineering would play an important role in optimizing the device parameters.