An Efficient FPGA Implementation of Binary Coded Decimal Digit Adders and Multipliers

Decimal arithmetic has gained high impact on the overall performance of today’s financial and commercial applications. Decimal arithmetic is pervasive in human-oriented applications but has a limited use in numerical data processing. Decimal additions and multiplication plays a main role in decimal operations which is used in any decimal arithmetic algorithm. Decimal digit adders and decimal digit multipliers are usually the building blocks for higher order decimal adders and multipliers. FPGAs provide an efficient hardware platform that can be employed for accelerating decimal algorithms. In this paper, different designs for two decimal digit adders and one decimal digit multiplier are proposed. The proposed designs were described, functionally tested, and implemented using VHDL and the Xilinx ISE 10.1 targeting Xilinx Vertix-5 XC5VLX30-3 FPGA. This design is mainly used to decrease the area and as well as increase the functioning speed. Implementation results and comparison with existing designs are provided.