Optimization of Memory Based LUT Multiplier

FIR filters are widely used as a basic tool in various signal and image processing applications, in which multipliers are key components of high performance FIR filters. The multiplier uses LUT’s as memory for their computations. A system’s performance is generally determined by the performance of the multiplier because the multiplier is generally the most area consuming. Hence optimizing area and memory of multiplier is the major design issue. Previously the anti-symmetric product coding (APC) and odd-multiple-storage (OMS) techniques were proposed for look-up-table (LUT) design. These techniques used for efficient. Memory-based multiplication. By using APC technique LUT size is reduced to half and by using OMS technique LUT size is further reduced to half. The combining technique of these two reduces the memory size to quarter of the conventional LUT size. In this paper the combined technique of APC and Optimized OMS is presented. As said earlier, APC reduces LUT size to half and our proposed optimized OMS reduces the size to one fourth of the conventional LUT. The combined approach of these two techniques reduces the size of LUT to 1/8 of the conventional LUT. Memory-based computing is well suited for many Digital signal processing (DSP) algorithms, which involve multiplication with a fixed set of coefficients.