FPGA-Based Processor Array Architecture for Profile Hidden Markov Models

This paper proposes novel processor array structure to speed up the Viterbi algorithm for Profile Hid- den Markov Models. This structure is amended to allow hardware reuse instead of repeating the pro- cessing elements of the processor array on multiple FPGAs. Also, it has the advantage of reducing the area overhead of the FPGA compared to the pre- viously reported processor array structure. There- fore, it increases the maximum number of Process- ing Elements (PEs) that could be implemented on the FPGA and hence increasing the throughput. FPGA implementation results show that the pro- posed design has a considerable higher speedup (up to 165%) over the previously reported one.