A NOVEL BOOTH WALLACE MULTIPLIER FOR DSP APPLICATIONS

Multipliers have great importance in both digital signal processors and microprocessors. So designing a high speed multiplier is the need of the hour. There are several methods available to speed up a multiplier. This paper incorporates pipelining technique to a multiplier for improving its performance. The multiplier under consideration is Booth Wallace multiplier. A comparison between pipelined and non-pipelined booth Wallace multiplier in terms of delay and area utilization were also done in this work. Verilog HDL has been used for the coding. Xilinx ISE 14.2 design suite is used for synthesizing the code.