An Optimized Parallel Mixcolumn and Subbytes design in Lightweight Advanced Encryption Standard

This paper presents a high speed, FPGA implementation of AES Encryption and Decryption (acronym for Advance Encryption Standard, also known as Rijndael Algorithm) in which the different steps of AES is applied in a parallel manner. This implementation can reduce the latency in which the process of implementation is reduced in a drastic manner. The paper deals with a comparison of the normal implementation of steps of AES and the parallel implementation. Inorder to increase the throughput of the AES encryption process the latency of the AES process should be reduced. Among Add Round Key, Sub Bytes, Shift Rows and Mix Columns, Sub Bytes and Mix Columns produce more latency. The execution delay of Mix Columns results in 60 percent of the total latency. Therefore Parallel Mix Columns is used inorder to reduce the latency. In this the block computes one column at a time such that the four columns are executed at the same time rather than each byte executing at a time. In Parallel Sub Bytes, four columns are executed at the same time rather than each byte executing at a time, this reduces the latency. Encryption is the process of encoding information so it cannot be read by hackers. The information is encrypted using algorithms and is converted into unreadable form, called cipher text. The authorized person will decode the information using decryption algorithms. The cryptography algorithms are of three types -symmetric cryptography (using 1 key for encryption/decryption), asymmetric cryptography (using 2 different keys for encryption/decryption), and cryptographic hash functions using no keys (the key is not a separate input but is mixed with the data).