Implementation of 64-Point Reconfigurable FFT Processor for ASIP Architecture

In this paper a novel architecture of ASIP for a reconfigurable FFT is proposed. The proposed design implements a reconfigurable 64 points FFT processor for unsigned real numbers. By changing the value of integer constant we can design 2, 4, 8, 16, 32 and 64 point FFT which incorporates a high speed ASIP. In OFDMA system there is a need of alterable point FFT processor. Hence, the design meets the requirement of OFDMA system. DIF - FFT algorithm is implemented using VHDL language and Xilinx 9.1i is used for s imulation results. The clock frequency is limited to 272.769 MHz for design stability and real time processing.