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An FPGA Based Floating Point Arithmetic Unit Using Verilog

Journal: International Journal for Modern Trends in Science and Technology (IJMTST) (Vol.2, No. 9)

Publication Date:

Authors : ; ;

Page : 53-57

Keywords : IJMTST; ISSN:2455-3778;

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Abstract

Floating Point (FP) multiplication is widely used in large set of scientific and signal processing computation. Multiplication is one of the common arithmetic operations in these computations. A high speed floating point double precision multiplier is implemented on a Virtex-6 FPGA. In addition, the proposed design is compliant with IEEE-754 format and handles over flow, under flow, rounding and various exception conditions. The design achieved the operating frequency of 414.714 MHz with an area of 648 slices.

Last modified: 2016-10-07 19:01:03