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Journal: International Journal of Engineering Sciences & Research Technology (IJESRT) (Vol.5, No. 11)

Publication Date:

Authors : ; ;

Page : 115-123

Keywords : Memory Built In Self - Test (MBIST); State Machine Controller (SMC); Reliability Enhancement Circuit (REC); Successive Read Detector (SRD); Defect - per Million (DPM) .;

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New memory technologies and processes introduce new defects that cause previously unknown faults. Dynamic faults are among these new faults; they can take place in the absence of the traditional static faults. Further shows based on industrial test results, the importance of such fau lts for the new memory technologies, and introduce a systematic way for modeling them. It concludes that current and future SRAM products need to consider testability for dynamic faults or leave substantial DPM and it sets a direction for further research. It therefore introduces a new test (March SS), with a test length of 22n that detects all realistic simple static faults and some of the Dynamic Faults in RAMs. This project not only describes detection of faults but also to repair the detected faults, si mply evaluates the improvement of RAM reliability in terms of the resistance value of the resistive - open defect and proposes a simple method for enhancing the reliability of static random access memories (SRAMs) with resistive open defects. This method pre vents a SRAM from executing successive multiple read operations on the same position, such that the hard - to - detect defects cannot manifest as functional faults. This can prolong the lifetime of the SRAM with latent hard - to - detect defects.

Last modified: 2016-11-07 18:02:54