An Analysis of Noble 12T SRAM cell with different performance parameter at 32 NM Technology

ABSTRACT Leakage power dissipation, read delay, write delay and ION/IOFF are initial parameters which are practically positive in low power applications. Now a day's low power applications are valuable in semiconductor devices. This paper presents a noble 12T SRAM cell where we use Schmitt trigger circuit and conventional transistor to augment cell performance. Firstly we analysis proposed 12T SRAM cell with conventional 6T, 9T, 10T and 11T SRAM cell in different parameters and compares them in 0.9 volt at 32nm technology. Results are enhanced inread delay, ION/IOFF, leakage current and power dissipation.