DESIGN OF 500 MHZ DELAY LOCKED LOOP USING 28NM CMOS TECHNOLOGY

This paper presents the design of low power and low area delay-locked loop (DLL) of 500 MHz output frequency and its layout design using 28nm High performance compact mobile computing (HPCP) CMOS technology. The architecture of the proposed DLL consist of a phase frequency detector (PFD), charge pump which uses a current source of 25uA, a first ordered low pass filter (LPF) of 650fF capacitance and voltage controlled delay lines (VCDL) which is designed using cascading of multiple current starved delay cells in a sequence to achieve at each stage 17.14 degrees spaced phase shift clock. The design challenge is to design and do layout of a 500MHz DLL using 0.9V supply in 28nm CMOS HPCP technology which consumes less current and low area. Another challenge is to perform the jitter analysis which mainly causes due to uncertainties in reference clock, charge pump current, Loop filter capacitance and voltage controlled delay cells. Using the Cadence spice simulator, simulation results for the post layout net list shows the stable 500 MHz clock output, at a control voltage of 513mV in a lock range. And the layout design shows the area occupied is approximate 1060 square microns and the power consumption of the entire DLL is 1.305mW.