Implementation of Dual-Precision Floating Point Multiplier on FPGA

FPGA’s have a generic nature of programmability and suppleness to implement during a wide selection of applications. However FPGA’s encompasses a non-specific nature towards the scientific applications whatever floating-point operations are needed. Floating purpose arithmetic operations consume great deal of space and its resources. Typically floating purpose operations involve addition, subtraction, multiplication, division and square root. During this paper, we tend to target quick multiplication that’s capable to perform either single precision operation or a double precision operation. These operations are designed to reduce the delay and space by reducing the amount of partial product generations. In this paper we tend to planned a way of Vedic multiplier method. This method shows the high performance of multiplier in embedded cores.