Optimisation of Delay and Power Consumption in Fin-FET SRAM Cells

ABSTRACT Static Random Access Memory (SRAM) comprises considerable proportion of total area and total power for almost all VLSI chips as cache memory for the System on Chip (SOC) and it is considered to be more intense in upcoming time in both handy devices and high-performance processors. By using low-power FinFET based SRAM cell, we can accomplish higher steadfastness and enhanced battery life for handy devices. Our objective of this work is to improve delay and power consumption in proposed nanoscale 7T FinFET SRAM cell structure. An additional transistor is implemented on FinFET 6T SRAM cell and results are analysed and compared with basic 6T FinFET and proposed 7T FinFET based cell structures on CADENCE VIRTUOSO tool at 45nm technology scale. The power consumption and write delay as well as read delay of proposed 7T FinFET based SRAM cell structure improves with reference to the 6T FinFET SRAM cell architecture.