DESIGN AND IMPLEMENTATION OF MOD-6 SYNCHRONOUS COUNTER USING VHDLJournal: ARID ZONE JOURNAL OF ENGINEERING, TECHNOLOGY AND ENVIRONMENT (Vol.9, No. 1)
Publication Date: 2013-08-01
Authors : P Y Dibal;
Page : 17-26
Keywords : VHDL; MOD-6 Synchronous counter; FPGA; Xilinx ISE; XC3S1000; Spartan-3;
This paper deals with the design of a MOD-6 synchronous counter using VHDL (VHSIC Hardware Description Language). The VHSIC stands for Very High Speed Integrated Circuit. Using this approach, the behaviour of the counter is the most important aspect of the design. In the first section, the paper introduced counters in general, and their areas of specialization, like frequency synthesizers. The synchronous counter was then introduced, stating the behaviour of the flip-flops that make the counter. The modulus of a counter was defined. In the second section, the Xilinx ISE (Integrated Simulation Environment) and the ISIM (Integrated Simulator) were presented and briefly described with their respective snapshots. The structure of a typical VHDL code was presented, which included LIBRARY, ENTITY, and ARCHITECTURE. Each of these structures was then briefly described. The main work in this paper was then presented. The count sequence steps were stated as 120â†'3â†'5â†'7â†'6â†'4"> . VHDL was used to model the counter to count through six steps, outputting count values according to desired steps. The hardware implementation of the design was presented, where the implementation process was described, with a supporting diagram, followed by the floor-planning technique, in which the PORTS described in the VHDL design were assigned to the physical pins of the XC3S1000 FPGA (Field Programmable Gate Array) chip. The final steps of the hardware implementation process were then presented. These include bitstream generation and download to target device. The third section of the paper presented the results obtained. Simulation/timing results of the design were presented, showing the output of the counter at each state with respect to the clock signal. The result of the synthesis of the design was presented, which showed the FPGA area with the exact location of the pins on the FPGA chip. Finally, the fourth section presented the conclusion arrived at, in respect of the design that was carried out.
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