Design of High Speed Area & Power Efficient Parallel Prefix Adders with QCA Majority Logic

As transistors reduce in size more and more of them can be accommodated in a one die, thus growing chip computational capabilities. However, transistors cannot find much lesser than their current size. The quantum-dot cellular automata (QCA) approach represents one of the possible solutions in overcoming this physical edge, level while the propose of logic modules in QCA is not always straight forward. In this brief, we propose some adder that out performs all state-of-the art competitors and achieves the best area-delay tradeoff.