DESIGN OF PHASE LOCKED LOOP

In this work, we have designed CDR-PLL for 1GHz frequency. The design is carried out in the 180nm CMOS technology. We have use Hogge phase detector with the Kim-Lee delay cell based VCO. The designed CDRPLL is tested by applying the 8B-10B encoded data and the simulation results are represented. The obtained results show that the clock is recovered successfully.