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Journal: International Journal of Engineering Sciences & Research Technology (IJESRT) (Vol.6, No. 12)

Publication Date:

Authors : ; ;

Page : 413-426

Keywords : Digital Hardware; SNR; RCA; Artix-7; FPGA; Xilinx; Verilog HDL.;

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Now a days at the receiving end in the applications of Cognitive Radio, Tele medicine, wireless networking, and in receiving system of multiple channels Electro Encephalo Gram (EEG) collected data, Wireless Brain Machine Interfacing Radio Frequency (RF) wireless data receiver system, and in RF Radar communication systems receiver's noise performance is very critical. For noise performance Signal to Noise Ratio (SNR) is a Key parameter. SNR has to be calculated right after the receiving of the data, or at the intermediary stages of the Digital Signal Processing of the system. In many of such systems one of the most important approaches is to have a dedicated hardware at the receiving end, where a DSP processor which processes the required data processing. In these Dedicated Digital Hardware systems SNR Hardware plays a critical role. In this research we have implemented Digital Hardware for a highly efficient Novel Signal to Noise Ratio (SNR) mechanism & it is a frequency domain SNR. Due to SNR hardware requirement in many advanced applications, and keeping in mind of the novel formula's efficiency, and as it has never been implemented in hardware we have got motivated towards implementing this SNR mechanism onto Xilinx Field Programmable Gate Arrays, especially to find its speed of operation and compatibility for the current ongoing technologies. In this research work we have developed two different types of architectures a) Sequential data processing architectures b) Parallel data processing architectures. During this hardware design we have developed a novel Full Adder (Faster Full Adder) for addition digital circuit, which makes the Ripple Carry Addition (RCA) process much faster than regular RCA process (Faster RCA). Parallel architectures are working faster than sequential architectures both in terms of total delay and clock speed, at the expense of somewhat more hardware and power utilization. Both architectures are working at high GHz rates than current real-time digital technologies sampling rates and system clock speeds, and hence are very useful for all ongoing real time technologies. These speeds are highly useful even for future real-time technologies. We did this implementation on Xilinx Artix-7 FPGAs using Xilinx Vivado 2015.2 Design suite. Verilog Hardware Description Language (HDL) is used for programming this hardware.

Last modified: 2017-12-19 19:52:58