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Clock Power Reduction Using Merged Flip Flops Technique.

Journal: International Journal of Engineering Sciences & Research Technology (IJESRT) (Vol.3, No. 4)

Publication Date:

Authors : ;

Page : 7039-7044

Keywords : Clock power reduction; merging; multi-bit flip flop; replacement; wire length.;

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The main constraint in any VLSI chip design are reducing power consumption and area and increasing speed. In this project my aim is to obtain reduced clock power by replacing single bit flip flops into multi bit flip flops. To perform a co-ordinate transformation, identify those flip flops that can be merged and their legal regions. The legal placement region of the flip flop can be obtained by the overlapped area of these regions and these regions are in the diamond shape, it is not easy to identify the overlapped area. The overlapped area can be identified more easily to get rectangular regions. To avoid wasting time in finding impossible combination of flip flops, first build a combination table before actually merging two flip flops. All possible combinations of flip flops in order to get a new multi-bit flip flops provided by the library. The flip flops can be merged with the help of the combination table. Then partition a chip in to several sub regions and perform replacement in each sub region to reduce the complexity. Then combine several bins into a larger bin and repeat this step until no flip flop can be merged any more. It is applicable for other low power design circuits such as counter and shift register which are used in data processing applications.

Last modified: 2014-05-13 19:15:01