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Voltage Controlled Delay Line with PFD for Delay Locked Loop in CMOS90nm Technology.

Journal: International Journal of Engineering Sciences & Research Technology (IJESRT) (Vol.3, No. 3)

Publication Date:

Authors : ; ; ;

Page : 1140-1144

Keywords : Conventional Analog DLL; Proposed PFDarchitecture Proposed VCDL architecture;

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Low power consumption is always desired for any electronic products today. Demand of modern measurement systems in submicron CMOS process introduced new challenges in design of low power high frequency clock generation systems. In the DLL Design, the performance of the VCDL is important part. Here the proposed architecture of VCDL can work at 1 GHz having different delay. In this paper, the proposedNOR based PFD have the better Jitter and Dead zone performance. The Jitter of the PFD is 76.4227 ps and Dead zone 32.3076 ps. The power consumption is 4.3530E-04 watts and having 20 transistors.

Last modified: 2014-05-20 22:05:50