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Leakage Current Reduction Techniques for CMOS Circuits.

Journal: International Journal of Engineering Sciences & Research Technology (IJESRT) (Vol.3, No. 3)

Publication Date:

Authors : ; ;

Page : 1363-1366

Keywords : Dual Vth; Transistor Stack; Sleep Transistor; Forced Transistor Stack; MTCMOS; VTCMOS; SCCMOS; LECTOR; GALEOR;

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Most of the portable systems, such as cellular communication devices, and laptop computers operate from a limited power supply. Devices like cell phones have long idle times and operate in standby mode when not in use. Consequently, the extension of battery- based operation time is a significant design goal which can be made possible by controlling the leakage current flowing through the CMOS gate. Leakage Current loss is a major concern in nanometer and deep submicron technologies. In this paper we use different techniques to reduce leakage power. Based on the surveyed techniques a designer is able to select appropriate leakage current reduction technique

Last modified: 2014-05-26 14:58:53