MOSFET Scaling and Small Geometry EffectsJournal: International Journal of Engineering Sciences & Research Technology (IJESRT) (Vol.3, No. 3)
Publication Date: 2014-03-30
Authors : Sanjeev Kumar Singh; Vishal Moyal;
Page : 1586-1590
Keywords : Silicon-on-Insulator (SOI); MOSFETs; Short-channel effects; modeling; Simulation;
There have been proposed several sets of “rules” for scaling, for the purpose of discovering as much as possible the electrical consequences of MOSFET size reduction. Principle am There have been proposed several sets of “rules” for scaling, for the purpose of discovering as much as possible the electrical ong these are rules by Dennard in 1974 (1 ?m channel length) and Baccarani in 1984 (0.25 ?m). By scaling, we hope to… -Increase packing density and chip functionality, Increase device current and speed. Lower cost (increase cost effectiveness). but the trade-offs are Mobility degradation due to increased vertical fields. Velocity saturation due to increased lateral fields, Charge sharing by drain (short channel effects; DIBL), Increased drain/source resistance due to reduced area for current flow.
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Last modified: 2014-06-16 20:21:35