A Novel Sense Amplifier Design for Efficient Memory Read Operation

Sense amplifier is one of the most important critical circuit in the periphery of CMOS memory array structure. It plays an important role in memory (SRAM and DRAM) read operation. The memory access time and overall memory power dissipation is greatly affected by the performance of sense amplifier. A novel 9T sense amplifier architecture is proposed in this paper which operates with less delay and low power. The sense amplifier proposed in the paper operates in two modes. In precharge mode the outputs get precharged to full supply voltage and in sensing mode sense amplifier comes to active state by enabling sense input. In sensing mode sense amplifier senses the output of the SRAM cell correctly during its read operation. Design metrics such as dynamic power, delay and power delay product, energy and energy delay product are taken into account. All the sense amplifiers were designed using SYNOPSYS EDA tool and simulated in 30nm technology. Simulation results shows that the proposed sense amplifier provides better performance than other conventional sense amplifiers.