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A 1.8V 8-bit 100-MS/s Pipeline ADC in 0.18μm CMOS Technology

Journal: International Journal of Science and Research (IJSR) (Vol.3, No. 5)

Publication Date:

Authors : ; ;

Page : 671-674

Keywords : ADC; Dynamic charge sharing Comparator; Folded Cascade OP-AMP;

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This paper authors have design of an 8-Bit Pipelined Analog-to-Digital Converter (ADC) which is realizing using 0.18?m CMOS technology. The simulation result is carried out in 0.18?m technology. The Supply voltage for this Pipelined ADC is ±1.8V for 0.18?m Technology. The Characterization of Pipelined ADC is done in terms of SNR, SFDR, FOM, power dissipation in 0.18?m CMOS technology. The Simulation Result Shows that the Sampling Rate is 200MS/s with power Dissipation of 20.2mW was achieved in 0.18?m technology. The measured SNR is 50.2dB, SFDR is 67.56dB and FOM is 35.16 uJ/conv-step in 0.18?m Technology.

Last modified: 2014-07-02 16:12:55