PRECISE CALCULATION UNIT BASED ON A HARDWARE IMPLEMENTATION OF A FORMAL NEURON IN A FPGA PLATFORM

The formal neuron is a processing unit that performs a number of complex mathematical operations on real format data. These calculation units require hardware’s architectures capable providing extremely accurate calculations treatments. To arrive upon more accurate hardware architecture in terms of the calculation, the new proposed method uses data coding in single precision floating point. This allows handling of infinitely small and infinitely large data and; consequently, a diverse field of application. The formal neuron implementation requires an embedded platform whose implementation must be flexible, efficient and fast. This article aims at presenting in detail a new precise method to implement this calculation unit. It uses a number of specific blocks described in VHDL hardware description language in an embedded FPGA platform. The data handled by these blocks are coded in 32-bit floating point. The implementation of this new method has been developed and tested on an embedded FPGA platform of Altera DE2-70. The calculation results on the platform and those obtained by simulation are very conclusive.