N-BIT CMOS Comparator with Zero Crossing Detector Using Parallel Prefix Tree

This paper provides an experience of new comparator model gives large range, with faster operation by converting n-bit CMOS cells. This comparator make use of novel scalable parallel prefix constructs strategic advantage by comparing Most Significant Bit (MSB) outcomes which is scheduled bit wise towards the Least Significant Bit (LSB). By comparing as the bits are equal and high speed zero detector circuit is used for decision power effectiveness is maintained over a wide range. More than this, the design uses a standard reconfigurable VLSI