DESIGN OF SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS USING VHDL ON CPLD BOARDJournal: Iord journal of science & technology (Vol.01, No. 02)
Publication Date: 2014-02-10
Authors : Priyanka D. Ambagade; Prof M S. Korde;
Page : 21-26
Keywords : : Quartus II; Altera; Altera Simulator; JTAG;
Today, every SSI and MSI function can be implemented with a CPLD (Complex Programmable Logic Device) using the VHDL codes. The design starts with entry through the VHDL code. The program is saved in the .svf file. For implementation of the digital circuit, the program is transferred to the CPLD via JTAG USB cable, using the ISP technique. This paper presents the technique of preparing the VHDL code for an 8-bit Sequence detector and a Mod-10 ripple counter circuits. The circuits have been successfully implemented with the CPLD chip and the simulation waveforms are obtained.
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Last modified: 2014-07-14 00:21:56