HIGH SPEED MULTI-LEVEL DISCRETE WAVELET TRANSFORM USING CANONIC SIGNED DIGIT TECHNIQUE

A few designs have been proposed for productive VLSI usage of 2-D DWT for continuous applications. It is discovered that multipliers expend more chip zone and builds unpredictability of the DWT engineering. Multiplier-less (M-less) equipment usage approach gives an answer for lessen chip zone, bring down equipment unpredictability and higher throughput of calculation of the DWT architecture. The proposed design outline is (i) priority must be given for memory complexity optimization over the arithmetic complexity optimization or reduction of cycle period and (ii) memory utilization efficiency to be considered ahead of memory reduction due to design complexity of memory optimization method. Based on the proposed design outline four separate design approaches and concurrent architectures are presented in this thesis for area-delay and power efficient realization of multilevel 2-D DWT. In this theory a M-less VLSI engineering is proposed utilizing new circulated math calculation named CSD. We show that CSD is an exceptionally effective design with adders as the primary part and free of ROM, duplication, and subtraction. The proposed engineering utilizing CSD gives less deferral and least number of cut looked at the current design. The simulation was performed using XILINX 14.1i and ModelSim simulator