Block Level Design Implementation of 100 Mbps Ethernet Telemetry using Vivado TEMAC IP core in Artix-7

ABSTRACT Telemetry is used to acquire data from a remote location and transfer to a location where it is analyzed. In sonar systems, data acquired is transmitted and received at desired location using Ethernet. Here the Ethernet data coming from a location is received and it is transmitted to another location as needed. Designs in which IPs are added as RTL source files are a little complex for the modern IP which has complex interfaces and port mappings. Block level design of the receiver- transmitter system is implemented using Vivado IPs integrator tool and is implemented on ARTIX 7 FPGA evaluation board. Vivado IP integrator tool integrates the complex IPs in a single step. Keywords: Ethernet, FPGA, UDP, Vivado, IP