TIME EFFICIENT PARITY GENERATOR BASED ON QUANTUM-DOT CELLULAR AUTOMATA

A parity generator is a circuit that generates redundant bits used for error detection and is used when transmitting binary information. Previous parity generator circuits based on quantum-dot cellular automata (QCA) are designed to reduce the area of the circuit. Input cells of existing circuit are designed inside the circuit and the circuit's signal is not propagated properly due to the influence between adjacent wires. In addition, existing circuits consume many clocks because the XOR gate, which is an essential component of the parity generator circuit, consumes many clocks. In order to solve this problem, we design a 3-bit odd parity generator circuit using QCA for fast operation. The proposed circuit uses an XOR gate that can operate one clock faster than the existing XOR gate to reduce the clock, and by extending this XOR gate, the output value can be obtained faster than the conventional circuit. In the proposed circuit, the result is verified through simulation and the performance is compared with the existing circuit.