POWER-DELAY EFFICIENT ASYNCHRONOUS DESIGN APPROACH USING GALEOR

Leakage power dissipation is a chief alarm in nanometer & deep submicron technologies. In CMOS circuits, leakage current has become major supplier to the whole power dissipation attributable to the unremitting trend of technology scaling. The main objective of this paper is to reduce leakage power dissipation with diverse leakage diminution techniques. We propound a novel seepage decline methodology named “Multi Threshold Null Convention Galeor” which can attain superior leakage power deduction analogize to the other techniques agitate in this paper. In order to extant the rendition of proffer approach, a full adder is schemed and there by demonstrate the power, delay, slew rate and energy. All 27 threshold standard cells are designed and simulated for low power performance; delay evaluation and is presented in this paper