A Novel Implementation of High Speed AES on Field Programmable Gate Array

We present an efficient hardware architecture design & implementation of Advanced Encryption Standard (AES) ? Rijndael cryptosystem. The AES algorithm defined by the National Institute of Standard and Technology (NIST) of United States has been widely accepted. All the cryptographic algorithms developed can be implemented with software or built with pure hardware. However with the help of Field Programmable Gate Arrays (FPGA) we tend to find expeditious solution and which can be easily upgraded to integrateany concordat changes. The s-box can be implemented using LUT, so the performance of the AES increases. This contribution investigates the AES encryption and decryption cryptosystem with regard to FPGA and Verilog. Optimized and Synthesizable Verilog code is developed for the implementation of both 128-bit data encryption and decryption process. Xilinx ISE 10.1 software is used for simulation. Each program is tested with some of the sample vectors provided by NIST and output results are perfect with minimal delay. The synthesis results found from FPGA implementation by Xilinx Synthesis Tool on Virtex II pro kit shows that the computation time for generating the ciphertext by AES with 4 sbox and 2 dual port RAM is 6.922 ns.