EFFICIENT GLOBAL ‘RAPID’ OPTIMIZATION OF ANALOG CIRCUITS: APPLICATION TO THE DESIGN OF A CMOS OPERATIONAL TRANSCONDUCTANCE AMPLIFIER

Main goals of analog circuit sizing optimization are to maximize circuits' performances within a reasonable computing time. This allows designers reducing the so-called time to market. Recently, it has been proven that the efficient global optimization (EGO) technique allows constructing accurate models of circuits (not only) performances. Evaluation of such analytical models is very fast when compared to the well-known inloop techniques. In this work we focus on adopting such EGO technique for the optimal design of ‘complex' analog CMOS circuits. The case of an operational transconductance amplifier sizing problems is considered. Comparison with two metaheuristic-based in loop sizing techniques (PSO and BSA) is provided to show efficiency and rapidity of the proposed EGO-based approach.