Design and Implementation of Power Efficient Turbo Decoder?

Turbo decoding is viewed as superior alternate decoding technique in communication system, the circuit complexity and power consumption of turbo decoder implementation can often be prohibitive for power constrained system. To address these issues a power efficient turbo decoder based on soft out viterbi algorithm is designed. SOVA based turbo decoder can be implemented with high throughput and less complexity, This project work is towards Design and ASIC implementation of turbo decoder Using TSMC 65nm library, RTL model for Decoder is developed using HDL and synthesized, targeting ASIC implementation, clock gating technique has been adopted to meet low power requirement.